sable − MIPS R2000 instruction simulator [ ]
simulates the R2000 architecture including all instructions, the translation lookaside buffer and the memory and cache interface. Additionally, simulates several simple external devices; a scheduling and profiling clock, a console terminal port and a disk controller. is designed as a programming aid for the developement of operating systems, ROM resident code and other stand-alone utilities. is the backend simulation engine with the user interface provided by a special version of the debugger, sdbx. The option is used to instruct to expect to communicate with via interprocess communication primitives. If the option is opmitted, presents a simple monitor mode user interface allowing the user to dump register and memory and to set breakpoints and execute a MIPS object module. For a synopsis of the monitor mode commands, run without any arguments and enter the help command. A typical session is conducted under a window manager such as which is provided in the standard software distribution. This allows multiplexing of input and output between sdbx and the sable console terminal. sdbx and sable must be started in the same directory since they use the file in the current directory to establish the IPC connection. This directory would normally be the source directory for program under test. begins execution with the simulation in the state of reset as defined by the R2000 architecture. Additionally, provides that both the instruction and data caches will be flushed with invalid data and that all physical memory is initialized to zero. A simple default reset handler is provided if no code is explicitly loaded at the reset vector. This handler is jump instruction to the entry point of the program under test. dbx(1), window(1) The branch and link instructions are not supported. The ROM boot exception vector bit in the status register is not supported, all exeception vector the the utlbmiss or general exception vector in K0 space. Only R2000 core instructions and coprocessor 0 instructions are simulated, coprocessor 1 (floating point) instructions are effectively null operations.  break;  case SP_SRA:  RD = RT >> SHAMT;  break;  case SP_SLLV:  RD = RT << (RS & 0x1f);  break;  case SP_