get_fpc_csr(3) — bsd — mips UMIPS RISC/os 5.01



FPC(3-BSD)          RISC/os Reference Manual           FPC(3-BSD)



NAME
     fpc: get_fpc_csr, set_fpc_csr, get_fpc_irr,w swapRM, swapINX
          - floating-point control registers

SYNOPSIS
     #include <mips/fpu.h>

     int getfpccsr()

     int setfpccsr(csr)
     int csr;

     int getfpcirr()

     int swapRM(x)
     int x;

     int swapINX(x)
     int x;

DESCRIPTION
     These routines are to get and set the floating-point control
     registers of MIPS floating-point units.  All of these rou-
     tines take and or return their values as 32 bit integers.

     The file <mips/fpu.h> contains unions for each of the con-
     trol registers. Each union contains a structure that breaks
     out the bit fields into the logical parts for each control
     register.  This file also contains constants for fields of
     the control registers.

     All implementations of MIPS floating-point have a control
     and status register and a implementation revsion register.
     The control and status register is returned by getfpccsr.
     The routine setfpccsr sets the control and status register
     and returns the old value.  The implementation revsion
     register is read-only and is returned by the routine
     getfpcirr.

     The routine swapRN sets only the rounding mode and returns
     the old rounding mode.  The routine swapINX sets only the
     sticky inexact bit and returns the old one.  The bits in the
     arguments and return values to swapRN and swapINX are right
     justified.

SEE ALSO
     R2010 Floating Point Coprocessor Architecture.








                        Printed 11/19/92                   Page 1
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