NAME

make − maintain, update, and regenerate related programs and files

SYNOPSIS

make [ −f makefile ] ... [ −d ] [ −dd ] [ −D ] [ −DD ] [ −e ] [ −i ] [ −k ] [ −n ] [ −p ] [ −P ]

[ −q ] [ −r ] [ −p ] [ −s ] [ −S ] [ −t ] [ target ... ] [ macro=value ... ]

DESCRIPTION

make executes a list of shell commands associated with each target, typically to create or update a file of the same name. makefile contains entries that describe how to bring a target up to date with respect to others on which it depends.  These prerequisite targets are called dependencies. Since each dependency is a target, it may have dependencies of its own.

Targets, dependencies, and sub-dependencies comprise a tree structure that make traces when deciding whether or not to rebuild a target. make recursively checks each target against its dependencies, beginning with the first target entry in makefile if none is supplied on the command line.  If, after processing its all of its dependencies, a target file is found either to be missing, or to be older than any of its dependency files, make rebuilds it.  Optionally with this version of make, a target can be treated as out-of-date when the commands used to generate it have changed. 

To build a given target, make executes the list of commands, called a rule. This rule may be listed explicitly in the target’s makefile entry, or it may be supplied implicitly by make. 

If no makefile is specified with a −f option:

• If there is an SCCS history file for makefile, make will attempt to extract and read the most recent version of that file. 

• If there is a file named makefile in the current directory, make will attempt to read that file. 

• If there is an SCCS history file for Makefile, make will attempt to extract and read the most recent version of that file. 

• If there is a file named Makefile in the current directory, make will attempt to read that file. 

If no target is specified on the command line, make uses the first target defined in makefile.

If a target has no makefile entry, or if its entry has no rule, make attempts to derive a rule by each of the following methods, in turn, until a suitable rule is found.  (Each method is described under USAGE below.) 

• Pattern matching rules. 

• Implicit rules, read in from a user-supplied makefile. 

• Standard implicit rules (also known as suffix rules), typically read in from the file /usr/include/make/default.mk. 

• SCCS extraction.  make extracts the most recent version from the SCCS history file (if any).  See the description of the ‘.SCCS_GET:’ special-function target for details. 

• The rule from the ‘.DEFAULT:’ target entry, if there is such an entry in the makefile. 

If there is no makefile entry for a target, if no rule can be derived for building it, and if no file by that name is present, make issues an error message and stops. 

OPTIONS

−f makefile
Use the description file makefile. A ‘−’ as the makefile argument denotes the standard input.  The contents of makefile, when present, override the standard set of implicit rules and predefined macros.  When more than one ‘−f  makefile’ argument pair appears, make uses the concatenation of those files, in order of appearance. 

−d Display the reasons why make chooses to rebuild a target; make displays any and all dependencies that are newer.  In addition, make displays options read in from the MAKEFLAGS environment variable. 

−dd Display the dependency check and processing in vast detail. 

−D Display the text of the makefiles read in. 

−DD Display the text of the makefiles, default.mk file, the state file, and all hidden-dependency reports. 

−e Environment variables override assignments within makefiles. 

−i Ignore error codes returned by commands.  Equivalent to the special-function target ‘.IGNORE:’. 

−k When a nonzero error status is returned by a command, abandon work on the current target, but continue with other branches that do not depend on that target. 

−n No execution mode.  Print commands, but do not execute them.  Even lines beginning with an @ are printed.  However, if a command line contains a reference to the $(MAKE) macro, that line is always executed (see the discussion of MAKEFLAGS in Reading Makefiles and the Environment). 

−p Print out the complete set of macro definitions and target descriptions. 

−P Report dependencies recursively to show the entire dependency hierarchy, without rebuilding any targets. 

−q Question mode.  make returns a zero or nonzero status code depending on whether or not the target file is up to date. 

−r Do not read in the default file. 

−s Silent mode.  Do not print command lines before executing them.  Equivalent to the special-function target ‘.SILENT:’. 

−S Undo the effect of the −k option.  Stop processing when a non-zero exit status is returned by a command. 

−t Touch the target files (bringing them up to date) rather than performing their rules.  This can be dangerous when files are maintained by more than one person.  When the .KEEP_STATE: target appears in the makefile, this option updates the state file just as if the rules had been performed. 

macro=value
Macro definition. This definition remains fixed for the make invocation.  It overrides any regular definition for the specified macro within the makefile itself, or in the environment.  However, this definition can still be overridden by conditional macro assignments and delayed macro assignments in target entries. 

USAGE

Refer to Doing More with SunOS: Beginner’s Guide and make in Programming Utilities and Libraries for tutorial information about make. 

Reading Makefiles and the Environment

When make first starts, it reads the MAKEFLAGS environment variable to obtain a list of flag (single-character) options.  Then it reads the command line for additional options that also take effect. 

Next, make reads in a default makefile that typically contains predefined macro definitions, target entries for implicit rules, and additional rules, such as the rule for extracting SCCS files.  If present, make uses the file default.mk in the current directory; otherwise it reads the file /usr/include/make/default.mk, which contains the standard definitions and rules.  Use the directive ‘include /usr/include/make/default.mk’.  in your local default.mk file to include them. 

Next, make imports variables from the environment (unless the −e option is in effect), treating them as defined macros.  Because make uses the most recent definition it encounters, a macro definition in the makefile normally overrides an environment variable of the same name.  When −e is in effect, however, environment variables are read in after all makefiles have been read.  In that case, the environment variable takes precedence over any makefile definition. 

Next, make reads the state file, .make.state in the local directory if it exists, and then any makefiles you specify with −f, or one of makefile or Makefile as described above. 

Finally, (after reading the environment if −e is in effect), make reads in any macro definitions from the command line.  These override macro definitions in the makefile and the environment both.  But, if there is a definition for the macro in a makefile used by a nested make command, that definition takes effect for the nested make, unless you use the −e option.  With −e, the nested make also uses the value set on the command line. 

make exports its environment variables to each command or shell that it invokes.  It does not export macros defined in the makefile.  If an environment variable is set, and a macro with the same name is defined on the command line, make exports its value as defined on the command line.  Unless −e is in effect, macro definitions within the makefile take precedence over those imported from the environment. 

The macros MAKEFLAGS, MAKE and SHELL are special cases.  See Special-Purpose Macros below, for details. 

Makefile Target Entries

A target entry has the following format:

target... [:|::] [dependency] ... [; command] ...

[command]
...

The first line contains the name of a target (or a space-separated list of target names), terminated with a colon or double colon.  This may be followed by a dependency, or a dependency list that make checks in order.  The dependency list may be terminated with a semicolon (;), which in turn can be followed by a Bourne shell command.  Subsequent lines in the target entry begin with a TAB, and contain Bourne shell commands.  These commands comprise a rule for building the target. 

Shell commands may be continued across input lines by escaping the NEWLINE with a backslash (\).  The continuing line must also start with a TAB. 

To rebuild a target, make expands macros, strips off initial TAB characters and either executes the command directly (if it contains no shell metacharacters), or passes each command line to a Bourne shell for execution. 

The first line that does not begin with a TAB or # begins another target or macro definition. 

Makefile Special Characters

Global

# Start a comment.  The comment ends at the next NEWLINE.  If the # follows the TAB in a command line, that line is passed to the shell (which also treats # as the start of a comment). 

include filename
If the word include appears as the first seven letters of a line and is followed by a SPACE or TAB, the string that follows is taken as a filename to interpolate at that line.  include files can be nested to a depth of no more than about 16. 

Targets and Dependencies

: Target list terminator.  Words following the colon are added to the dependency list for the target or targets.  If a target is named in more than one colon-terminated target entry, the dependencies for all its entries are added to form that target’s complete dependency list. 

:: Target terminator for alternate dependencies.  When used in place of a ‘:’ the double-colon allows a target to be checked and updated with respect to alternate dependency lists.  When the target is out-of-date with respect to dependencies listed in one entry, it is built according to the rule for that entry.  When out-of-date with respect to dependencies in an alternate entry, it is built according the rule in that alternate entry.  Implicit rules do not apply to double-colon targets; you must supply a rule for each entry.  If no dependencies are specified, the rule is always performed. 

target [+ target...] :
Target group. The rule in the target entry builds all the indicated targets as a group.  It is normally performed only once per make run, but is checked for command dependencies every time a target in the group is encountered in the dependency scan. 

% Pattern matching rule wild card character.  Like the ∗ shell wild card, % matches any string of zero or more characters occurring in both a target and the name of a dependency file.  See Pattern Matching Rules, below for details. 

Macros

= Macro definition.  The word to the left of this character is the macro name; words to the right comprise its value.  Leading white space between the = and the first word of the value is ignored.  A word break following the = is implied.  Trailing white space is included in the value. 

$ Macro reference.  The following character, or the parenthesized or bracketed string, is interpreted as a macro reference: make expands the reference (including the $) by replacing it with the macro’s value. 

( )

{ } Macro-reference name delimiters.  A parenthesized or bracketed word appended to a $ is taken as the name of the macro being referred to.  Without the delimiters, make recognizes only the first character as the macro name. 

$$ A reference to the dollar-sign macro, the value of which is the character ‘$’.  Used to pass variable expressions beginning with $ to the shell, to refer to environment variables which are expanded by the shell, or to delay processing of dynamic macros within the dependency list of a target, until that target is actually processed. 

+= When used in place of ‘=’, appends a string to a macro definition (must be surrounded by white space, unlike ‘=’). 

:= Conditional macro assignment.  When preceded by a list of targets with explicit target entries, the macro definition that follows takes effect when processing only those targets, and their dependencies. 

Rules

− make ignores any nonzero error code returned by a command line for which the first non-TAB character is a ‘−’.  This character is not passed to the shell as part of the command line.  make normally terminates when a command returns nonzero status, unless the −i or −k options, or the .IGNORE: special-function target is in effect. 

@ If the first non-TAB character is a @, make does not print the command line before executing it.  This character is not passed to the shell. 

?  Escape command-dependency checking.  Command lines starting with this character are not subject to command dependency checking. 

!  Force command-dependency checking.  Command-dependency checking is applied to command lines for which it would otherwise be suppressed.  This checking is normally suppressed for lines that contain references to the ‘?’ dynamic macro (for example, ‘$?’). 

When any combination of ‘−’, ‘@’, ‘?’, or ‘!’ appear as the first characters after the TAB, all apply.  None are passed to the shell. 

Special-Function Targets

When incorporated in a makefile, the following target names perform special-functions:

.DEFAULT:
If it has an entry in the makefile, the rule for this target is used to process a target when there is no other entry for it, no rule for building it, and no SCCS history file from which to extract a current version.  make ignores any dependencies for this target. 

.DONE:
If defined in the makefile, make processes this target and its dependencies after all other targets are built. 

.IGNORE:
Ignore errors. When this target appears in the makefile, make ignores non-zero error codes returned from commands. 

.INIT:
If defined in the makefile, this target and its dependencies are built before any other targets are processed.

.KEEP_STATE:
If this target appears in the makefile, make updates the state file, .make.state, in the current directory.  This target also activates command dependencies, and hidden dependency checks. 

.MAKE_VERSION:
A target-entry of the form:

.MAKE_VERSION:  VERSION−number

enables version checking.  If the version of make differs from the version indicated, make issues a warning message. 

.PRECIOUS:
List of files not to delete. make does not remove any of the files listed as dependencies for this target when interrupted.  make normally removes the current target when it receives an interrupt. 

.SCCS_GET:
This target contains the rule for extracting the current version of an SCCS file from its history file.  To suppress automatic extraction, add an entry for this target, with an empty rule to your makefile. 

.SILENT:
Run silently. When this target appears in the makefile, make does not echo commands before executing them. 

.SUFFIXES:
The suffixes list for selecting implicit rules (see The Suffixes List). 

In this version of make, you can clear the definition of any special target, or any target starting with ‘.’, by supplying a target entry for it with an empty rule and empty dependency list;  the entry:

.special:

removes the definition of target named .special. 

Command Dependencies

When the ‘.KEEP_STATE:’ target appears in the makefile, make checks the command for building a target against the state file, .make.state.  If the command has changed since the last make run, make rebuilds the target. 

Hidden Dependencies

When the ‘.KEEP_STATE:’ target appears in the makefile, make reads reports from cpp(1) and other compilation processors for any “hidden” files, such as #include files.  If the target is out of date with respect to any of these files, make rebuilds it. 

Macros

Entries of the form

macro=value

define macros.  macro is the name of the macro, and value, which consists of all characters up to a comment character or unescaped NEWLINE, is the value. 

Subsequent references to the macro, of the forms: $(name) or ${name} are replaced by value. The parentheses or brackets can be omitted in a reference to a macro with a single-character name.

Macro definitions can contain references to other macros, in which case nested references are expanded first. 

Suffix Replacement Macro References

Substitutions within macros can be made as follows:

$(name:string1=string2)

where string1 is either a suffix, or a word to be replaced in the macro definition, and string2 is the replacement suffix or word.  Words in a macro value are separated by SPACE, TAB, and escaped NEWLINE characters. 

Pattern Replacement Macro References

Pattern matching replacements can also be applied to macros, with a reference of the form:

$(name: op%os= np%ns)

where op is the existing (old) prefix and os is the existing (old) suffix, np and ns are the new prefix and new suffix, respectively, and the pattern matched by % (a string of zero or more characters), is carried forward from the value being replaced.  For example:

PROGRAM=fabricate
DEBUG= $(PROGRAM:%=tmp/%−g)

sets the value of DEBUG to tmp/fabricate−g. 

Note: pattern replacement macro references cannot be used in the dependency line of a pattern matching rule; the % characters are not evaluated independently. 

Appending to a Macro

Words can be appended to macro values as follows:

macro += word ...

The space preceding the + is required.  make inserts a leading space between the previous value and the first appended word. 

Special-Purpose Macros

When the MAKEFLAGS variable is present in the environment, make takes flag (single-character) options from it, in combination with options entered on the command line.  make retains this combined value as the MAKEFLAGS macro, and exports it automatically to each command or shell it invokes. 

Note: flags passed with MAKEFLAGS are only displayed when the −d, or −dd options are in effect. 

The MAKE macro is another special case.  It has the value make by default, and temporarily overrides the −n option for any line in which it is referred to.  This allows nested invocations of make written as:

$(MAKE) ...

to run recursively, with the −n flag in effect for all commands but make.  This lets you use ‘make −n’ to test an entire hierarchy of makefiles. 

For compatibility with the 4.2 BSD make, the MFLAGS macro is set from the MAKEFLAGS variable by prepending a ‘−’.  MFLAGS is not exported automatically. 

The SHELL macro, when set to a single-word value such as /usr/bin/csh, indicates the name of an alternate shell to use.  Note: make executes commands containing no shell metacharacters directly.  Builtin commands, such as dirs in the C shell, are not recognized unless the command line includes a metacharacter (for instance, a semicolon).  This macro is neither imported from, nor exported to the environment, regardless of −e.  To be sure it is set properly, you must define this macro within every makefile that requires it. 

The KEEP_STATE environment variable, has the same effect as the ‘.KEEP_STATE:’ special-function target, enabling command dependencies, hidden dependencies and writing of the state file. 

Predefined Macros

make supplies the macros shown in the table that follows for compilers and their options, host architectures, and other commands. 

Table of Predefined Macros
Use	Macro	Default Value
Library	AR	ar
Archives	ARFLAGS	rv
Assembler	AS	as
Commands	ASFLAGS
	COMPILE.s	$(AS)  $(ASFLAGS)  $(TARGET_MACH)
	COMPILE.S	$(CC)  $(ASFLAGS)  $(CPPFLAGS)  $(TARGET_MACH) −c
C Compiler	CC	cc
Commands	CFLAGS
	CPPFLAGS
	COMPILE.c	$(CC)  $(CFLAGS)  $(CPPFLAGS)  $(TARGET_ARCH) −c
	LINK.c	$(CC)  $(CFLAGS)  $(CPPFLAGS)  $(LDFLAGS)  $(TARGET_ARCH)
FORTRAN 77	FC	f77
Compiler	FFLAGS
Commands	COMPILE.f	$(FC)  $(FFLAGS)  $(TARGET_ARCH) −c
	LINK.f	$(FC)  $(FFLAGS)  $(TARGET_ARCH)  $(LDFLAGS)
	COMPILE.F	$(FC)  $(FFLAGS)  $(CPPFLAGS)  $(TARGET_ARCH) −c
	LINK.F	$(FC)  $(FFLAGS)  $(CPPFLAGS)  $(LDFLAGS)  $(TARGET_ARCH)
Link Editor	LD	ld
Command	LDFLAGS
lex	LEX	lex
Command	LFLAGS
	LEX.l	$(LEX)  $(LFLAGS) −t
lint	LINT	lint
Command	LINTFLAGS
	LINT.c	$(LINT)  $(LINTFLAGS)  $(CPPFLAGS)  $(TARGET_ARCH)
Modula 2	M2C	m2c
Commands	M2FLAGS
	MODFLAGS
	DEFFLAGS
	COMPILE.def	$(M2C)  $(M2FLAGS)  $(DEFFLAGS)  $(TARGET_ARCH)
	COMPILE.mod	$(M2C)  $(M2FLAGS)  $(MODFLAGS)  $(TARGET_ARCH)
Pascal	PC	pc
Compiler	PFLAGS
Commands	COMPILE.p	$(PC)  $(PFLAGS)  $(CPPFLAGS)  $(TARGET_ARCH) −c
	LINK.p	$(PC)  $(PFLAGS)  $(CPPFLAGS)  $(LDFLAGS)  $(TARGET_ARCH)
Ratfor	RFLAGS
Compilation	COMPILE.r	$(FC)  $(FFLAGS)  $(RFLAGS)  $(TARGET_ARCH) −c
Commands	LINK.r	$(FC)  $(FFLAGS)  $(RFLAGS)  $(TARGET_ARCH)  $(LDFLAGS)
rm	RM	rm −f
Command
yacc	YACC	yacc
Command	YFLAGS
	YACC.y	$(YACC)  $(YFLAGS)
Suffixes	SUFFIXES	.o .c .c~ .s .s~ .S .S~ .ln .f .f~ .F .F~ .l .l~ .mod .mod~ .sym .def .def~ .p .p~ .r .r~ .y .y~ .h .h~ .sh .sh~ .cps .cps~
List

Unless these macros are read in as environment variables, their values are not exported by make.  If you run make with any of these set in the environment, it is a good idea to add commentary to the makefile to indicate what value each is expected to take.  If −r is in effect, make does not supply these macro definitions. 

Dynamic Macros

There are several dynamically maintained macros that are useful as abbreviations within rules.  They are shown here as references; it is best not to define them explicitly. 

$∗ The basename of the current target, derived as if selected for use with an implicit rule.  In the case of pattern matching rules, the value is the string matched by the ‘%’. 

$< The name of a dependency file, derived as if selected for use with an implicit rule. 

$@ The name of the current target. 

$?  The list of dependencies that are newer than the target, derived as if selected for use with an implicit rule.  Command-dependency checking is automatically suppressed for lines that contain this macro, just as if the command had been prefixed with a ‘?’.  See the description of ‘?’, under Makefile Special Tokens, above.  You can force this check with the !  command-line prefix. 

$% The name of the library member being processed.  See Library Maintenance for more information. 

To refer to a dynamic macro within a dependency list, precede the reference with an additional ‘$’ character (for example, ‘$$<’).  Because make assigns $< and $∗ as it would for implicit rules (according to the suffixes list and the directory contents), they may be unreliable when used within explicit target entries. 

All of these macros but $?  can be modified to apply either to the filename part, or the directory part of the strings they stand for, by adding an upper case F or D, respectively (and enclosing the resulting name in parentheses or braces).  Thus, ‘$(@D)’ refers to the directory part of the string ‘$@’; if there is no directory part, ‘.’ is assigned.  $(@F) refers to the filename part. 

Implicit Rules

When a target has no entry in the makefile, make attempts to determine its class (if any) and apply the rule for that class.  An implicit rule describes how to build any target of a given class, from an associated dependency file.  The class of a target can be determined either by a pattern, or by a suffix; there must also be a dependency file (with the same basename) from which such a target might be built.  In addition to a predefined set of implicit rules, make allows you to define your own, either by pattern, or by suffix. 

Pattern Matching Rules

A target entry of the form:

Tp%Ts: Dp%Ds
rule

where Tp is a target prefix, Ts is a target suffix, Dp is a dependency prefix, and Ds is a dependency suffix (any of which may be null), pattern matching rule in which the % stands for a basename of zero or more characters that is matched in both a filename and a dependency.  When make encounters a match in its search for an implicit rule, it uses the rule in that target entry to build the target from the dependency file.  Pattern-matching implicit rules typically make use of the $@ and $< dynamic macros as placeholders for the target and dependency names.  The dynamic macro $∗ is set to the string matched by the % wild card. 

Suffix Rules

When no pattern matching rule applies, make checks the target name to see if it contains a suffix in the known suffixes list.  If so, make checks for any suffix rules, as well as a dependency file with same root and another recognized suffix, from which to build it. 

The target entry for a suffix rule takes the form:

DsTs:
rule

where Ts is the suffix of the target, Ds is the suffix of the dependency file, and rule is the rule for building a target in the class.  Both Ds and Ts must appear in the suffixes list. 

A suffix rule with only one suffix describes how to build a target having a null (or no) suffix from a dependency file with the indicated suffix.  For instance, the .c rule could be used to build an executable program named file from a C source file named ‘file.c’. 

Table of Standard Implicit (Suffix) Rules
Use	Implicit Rule Name	Command Line
Assembly	.s.o	$(COMPILE.s) −o  $@ $<
	.s.a	$(COMPILE.s) −o  $% $<
		$(AR)  $(ARFLAGS)  $@ $%
		$(RM)  $%
Files	.S.o	$(COMPILE.S) −o  $@ $<
	.S.a	$(COMPILE.S) −o  $% $<
		$(AR)  $(ARFLAGS)  $@ $%
		$(RM)  $%
C	.c	$(LINK.c) −o  $@ $< $(LDLIBS)
Files	.c.ln	$(LINT.c)  $(OUTPUT_OPTION) −i $<
	.c.o	$(COMPILE.c)  $(OUTPUT_OPTION)  $<
	.c.a	$(COMPILE.c) −o  $% $<
		$(AR)  $(ARFLAGS)  $@ $%
		$(RM)  $%
FORTRAN 77	.f	$(LINK.f) −o  $@ $< $(LDLIBS)
Files	.f.o	$(COMPILE.f)  $(OUTPUT_OPTION)  $<
	.f.a	$(COMPILE.f) −o  $% $<
		$(AR)  $(ARFLAGS)  $@ $%
		$(RM)  $%
	.F	$(LINK.F) −o  $@ $< $(LDLIBS)
	.F.o	$(COMPILE.F)  $(OUTPUT_OPTION)  $<
	.F.a	$(COMPILE.F) −o  $% $<
		$(AR)  $(ARFLAGS)  $@ $%
		$(RM)  $%
lex	.l	$(RM)  $∗.c
Files		$(LEX.l)  $< > $∗.c
		$(LINK.c) −o  $@ $∗.c $(LDLIBS)
		$(RM)  $∗.c
	.l.c	$(RM)  $@
		$(LEX.l)  $< > $@
	.l.ln	$(RM)  $∗.c
		$(LEX.l)  $< > $∗.c
		$(LINT.c) −o  $@ −i $∗.c
		$(RM)  $∗.c
	.l.o	$(RM)  $∗.c
		$(LEX.l)  $< > $∗.c
		$(COMPILE.c) −o  $@ $∗.c
		$(RM)  $∗.c
Modula 2	.mod	$(COMPILE.mod) −o  $@ −e $@ $<
Files	.mod.o	$(COMPILE.mod) −o  $@ $<
	.def.sym	$(COMPILE.def) −o  $@ $<
NeWS	.cps.h	cps $∗.cps
Pascal	.p	$(LINK.p) −o  $@ $< $(LDLIBS)
Files	.p.o	$(COMPILE.p)  $(OUTPUT_OPTION)  $<
Ratfor	.r	$(LINK.r) −o  $@ $< $(LDLIBS)
Files	.r.o	$(COMPILE.r)  $(OUTPUT_OPTION)  $<
	.r.a	$(COMPILE.r) −o  $% $<
		$(AR)  $(ARFLAGS)  $@ $%
		$(RM)  $%

Table of Standard Implicit (Suffix) Rules
Use	Implicit Rule Name	Command Line
Shell	.sh	cat $< >$@
Scripts		chmod +x $@
yacc	.y	$(YACC.y) $<
Files		$(LINK.c) −o $@ y.tab.c $(LDLIBS)
		$(RM) y.tab.c
	.y.c	$(YACC.y) $<
		mv y.tab.c $@
	.y.ln	$(YACC.y) $<
		$(LINT.c) −o $@ −i y.tab.c
		$(RM) y.tab.c
	.y.o	$(YACC.y) $<
		$(COMPILE.c) −o $@ y.tab.c
		$(RM) y.tab.c

make reads in the standard set of implicit rules from the file /usr/include/make/default.mk, unless −r is in effect, or there is a default.mk file in the local directory that does not include it. 

The Suffixes List

The suffixes list is given as the list of dependencies for the ‘.SUFFIXES:’ special-function target.  The default list is contained in the SUFFIXES macro (See Table of Predefined Macros for the standard list of suffixes).  You can define additional ‘.SUFFIXES:’ targets; a .SUFFIXES target with no dependencies clears the list of suffixes.  Order is significant within the list; make selects a rule that corresponds to the target’s suffix and the first dependency-file suffix found in the list.  To place suffixes at the head of the list, clear the list and replace it with the new suffixes, followed by the default list:

.SUFFIXES:
.SUFFIXES: suffixes $(SUFFIXES)

A tilde (~) indicates that if a dependency file with the indicated suffix (minus the ~) is under SCCS its most recent version should be extracted, if necessary, before the target is processed. 

Library Maintenance

A target name  of the form:

lib(member ...)

refers to a member, or a space-separated list of members, in an ar(1V) library. 

The dependency of the library member on the corresponding file must be given as an explicit entry in the makefile.  This can be handled by a pattern matching rule of the form:

lib(%.s): %.s

where .s is the suffix of the member; this suffix is typically .o for object libraries. 

A target name of the form

lib((symbol))

refers to the member of a randomized object library (see ranlib(1)) that defines the entry point named symbol.

Command Execution

Command lines are executed one at a time, each by its own process or shell.  Shell commands, notably cd, are ineffectual across an unescaped NEWLINE in the makefile.  A line is printed (after macro expansion) just before being executed.  This is suppressed if it starts with a ‘@’, if there is a ‘.SILENT:’ entry in the makefile, or if make is run with the −s option.  Although the −n option specifies printing without execution, lines containing the macro $(MAKE) are executed regardless, and lines containing the @ special character are printed.  The −t (touch) option updates the modification date of a file without executing any rules.  This can be dangerous when sources are maintained by more than one person. 

To use the Bourne shell if control structure for branching, use a command line of the form:

if expression ; \
then command ; \
... ; \
else ; \
... ; \
fi

Although composed of several input lines, the escaped NEWLINE characters insure that make treats them all as one (shell) command line. 

To use the Bourne shell for control structure for loops, use a command line of the form:

for var in list ; \
do command; \
... ; \
done

To write shell variables, use double dollar-signs ($$).  This escapes expansion of the dollar-sign by make. 

Signals

INT and QUIT signals received from the keyboard halt make and remove the target file being processed unless that target is in the dependency list for ‘.PRECIOUS:’. 

EXAMPLES

This makefile says that pgm depends on two files a.o and b.o, and that they in turn depend on their corresponding source files (a.c and b.c) along with a common file incl.h:

pgm: a.o b.o
cc a.o b.o −o $@

a.o: incl.h a.c
cc −c a.c

b.o: incl.h b.c
cc −c b.c

The following makefile uses implicit rules to express the same dependencies:

pgm: a.o b.o
cc a.o b.o −o pgm

a.o b.o: incl.h

FILES

makefile

Makefile current version(s) of make description file

SCCS/s.makefile

SCCS/s.Makefile SCCS history files for the above makefile(s)

default.mk default file for user-defined targets, macros, and implicit rules

/usr/include/make/default.mk
makefile for standard implicit rules and macros (not read if default.mk is)

.make.state state file in the local directory

.make.state.lock lock file used for controlling write access to the state file

SEE ALSO

ar(1V), cc(1V), cd(1), get(1), lex(1), ranlib(1), sh(1)

Doing More with SunOS: Beginner’s Guide
Programming Utilities and Libraries

DIAGNOSTICS

make returns a exit status of 1 when it halts as a result of an error.  Otherwise it returns and exit status of 0. 

Do not know how to make target. Stop.
There is no makefile entry for target, and none of make’s implicit rules apply (there is no dependency file with a suffix in the suffixes list, or the target’s suffix is not in the list). 

∗∗∗ target removed.
make was interrupted while building target. Rather than leaving a partially-completed version that is newer than its dependencies, make removes the file named target.

∗∗∗ target not removed.
make was interrupted while building target and target was not present in the directory. 

∗∗∗ target could not be removed, reason
make was interrupted while building target, which was not removed for the indicated reason.

Read of include file ‘file’ failed
The makefile indicated in an include directive was not found, or was inaccessible. 

Loop detected when expanding macro value ‘macro’
A reference to the macro being defined was found in the definition.

Could not write state file ‘file’
You used the .KEEP_STATE: target, but do not have write permission on the state file. 

∗∗∗ Error code n
The previous shell command returned a nonzero error code.

∗∗∗ signal message
The previous shell command was aborted due to a signal.  If − core dumped appears after the message, a core file was created. 

BUGS

Some commands return nonzero status inappropriately; to overcome this difficulty, prefix the offending command line in the rule with a ‘−’. 

Filenames with the characters =, :, or @, do not work. 

You cannot build file.o from lib(file.o). 

Options supplied by MAKEFLAGS should be reported for nested make commands.  Use the −d option to find out what options the nested command picks up from MAKEFLAGS. 

This version of make is incompatible in certain respects with previous versions:

• The −d option output is much briefer in this version.  −dd now produces the equivalent voluminous output. 

• make attempts to derive values for the dynamic macros ‘$∗’, ‘$<’, and ‘$?’, while processing explicit targets.  It uses the same method as for implicit rules; in some cases this can lead either to unexpected values, or to an empty value being assigned.  (Actually, this was true for earlier versions as well, even though the documentation stated otherwise.) 

• make no longer searches the current directory for sccs history files. 

• Suffix replacement in macro references is now applied after the macro is expanded. 

There is no guarantee that makefiles created for this version of make will work with earlier versions. 

If there is no default.mk file in the current directory, and the file /usr/include/make/default.mk is missing, make stops before processing any targets.  To force make to run anyway, create an empty default.mk file in the current directory. 

Once a dependency is made, make assumes the dependency file is present for the remainder of the run.  If a rule subsequently removes that file and future targets depend on its existence, unexpected errors may result. 

When hidden dependency checking is in effect, the $?  macro’s value includes the names of hidden dependencies.  This can lead to improper filename arguments to compiler commands when $?  is used in a rule. 

Pattern replacement macro references cannot be used in the dependency line of a pattern matching rule. 

Unlike previous versions, this version of make strips a leading ‘./’ from the value of the ‘$@’ dynamic macro. 

Sun Release 4.0  —  Last change: 4 February 1988