NAME

mvme197 − MVME197 CPU

DESCRIPTION

The mvme197 is a CPU platform with one or more MC88110 MPUs.  The 197LE contains a single MC88110, and can be configured with 32 or 64 MB dual-ported onboard memory mezzanines up to a maximum of 192 MB.  The 197SP contains a single MC88110, can be configured with 128 or 256 MB dual-ported onboard memory mezzanines up to a maximum of 1.2 GB, and contains 256 KB of Secondary Cache driven by an MC88410 Secondary Cache Controller.  The 197DP contains two MC88110’s, can be configured with 128 or 256 MB dual-ported onboard memory mezzanines up to a maximum of 1.2 GB, and contains 256 KB of Secondary Cache driven by an MC88410 for each processor.  All of the mvme197 boards have 8 KB of battery backup static RAM, a time-of-day clock/calendar, an Ethernet transceiver interface (Intel 82596CA), four EIA-232-D serial communication ports (Cirrus Logic CD2400/2401), a SCSI-2 bus interface with DMA (NCR 53C710), a Centronics-compatible parallel printer port, configurable local and VMEbus address maps, six tick timers, and four ROM sockets of which two contain the MVME197BUG Debugger and Diagnostic Package. 

SPECIAL CONSIDERATIONS

The mvme197 uses five integrated circuits for controlling the VMEbus interface (vmechip2), peripheral interrupts (pccchip2), local bus (busswitch), and local memory (dcam and ecdm).  Unless otherwise specified, the configurable registers which control the memory, peripheral, or VMEbus interfaces are unchanged from what is described in the MVME197BUG User’s Manual.  This section describes those registers which are different from the ROM debugger settings. 

The vmechip2 controls the local bus to VMEbus requester.  It is set so that VMEbus FAIR mode arbitration is used, the VMEbus is released when the transaction is completed, and the VMEbus request level has the value configured in the mvmecpu master.d file.  The bus grant timeout timer is enabled, VMEbus access timeout value is set to 32 milliseconds, the VMEbus global timeout value is set to 256 microseconds, and the local bus timeout value is set to 8 microseconds. 

The vmechip2 also controls various I/O related operations, a set of general purpose timers, and VMEbus interrupts.  Both timers’ registers on the vmechip2 are initialized to zero.  The board control register is cleared, and the VMEbus control register word (0xFFF40048) has the MCLR bit (bit 11) set to 1 and all other bits reset to zero.  The RESET button, ABORT, ACFAIL, write posting, parity, and all VMEbus interrupt levels are enabled.  VMEbus interrupt request levels 1 through 7 are mapped to local interrupt request levels 1 through 7.  The VMEX and VMEY interrupt vectors (used for interrupts generated by the vmechip2 itself) are set based on the interrupt vector values in the VMEX and VMEY entries of the edt_data file. 

The pccchip2 controls all onboard peripherals.  The high order 4 bits of the interrupt vector used by each of the onboard devices is set based on the interrupt vector level specified for the PCC2 module in the edt_data file.  The two timers on the pcchip2 are initialized to an OFF state.  General purpose I/O interrupts are disabled. 

The busswitch provides an interconnect path between the MC88110 bus and an MC68040 compatible bus. This simplifies interfacing to the MC88110 in general, since it is easier to interface to a 32-bit data bus than to the MC88110’s 64-bit data bus.  The busswitch also provides two timers, one of which is used as the system tick timer (which usually runs at 100 MHz), and the other is used for kernel profiling. 

Each memory mezzanine is controlled by a dcam (DRAM Controller and Address Multiplexor) and four ecdm’s (Error Correction Data Multiplexor).  The dcam provides address decoding, DRAM timing, and control of the ecdm chips. The ecdm provides an advanced Error Detection And Correction (EDAC) system that provides single-bit correction of data errors independently for each ecdm. 

FILES

/dev/conctl
/dev/console
/dev/contty
/dev/contty??
/dev/dsk/m197_c0d?s?
/dev/e1x7_c0d0
/dev/generic/m197_c0d?
/dev/nvr∗
/dev/printer/lp197_c0d0
/dev/rdsk/m197_c0d?s?
/dev/rmt/m197_c0d?
/dev/xedt/lp1x7_c0
/dev/xedt/scsi1x7_c0

SEE ALSO

dcon(1M), mvmecpu(1M), scsi1x7(1M), console(7), cons1x7(7), e1x7(7), enet1x7(7), lp1x7(7), nvram(7), scsi1x7(7).