NAME

mvme187 − MVME187 CPU

DESCRIPTION

The mvme187 is a CPU platform with an MC88100 MPU, two MC88200 CMMUs, 32, 40, 48, or 64 MB of dual-ported onboard (mezzanine) memory, 8 KB of battery backup static RAM, 128 Kb of volatile static RAM, a time-of-day clock/calendar, an Ethernet transceiver interface (Intel 82596CA), four EIA-232-D serial communication ports (Cirrus Logic CD2400/2401), a SCSI-2 bus interface (NCR 53C710), a Centronics-compatible parallel printer port (except on M8120 systems), configurable local and VMEbus address maps, four tick timers, and four ROM sockets of which two contain the MVME187BUG Debugger and Diagnostic Package.  In addition, M8120 systems contain an additional Cirrus Logic CD2400 chip from which two additional serial communication ports are exposed. 

SPECIAL CONSIDERATIONS

The mvme187 uses three integrated circuits for controlling the VMEbus interface (vmechip2), peripheral interrupts (pccchip2), and local memory (memc040).  Unless otherwise specified, the configurable registers which control the memory, peripheral, or VMEbus interfaces are unchanged from what is described in the MVME187BUG User’s Manual.  This section describes those registers which are different from the ROM debugger settings. 

The vmechip2 provides a mechanism for mapping onboard memory to the VMEbus (VMEbus accesses to this memory are issued on the local bus) and it provides mechanisms for mapping VMEbus addresses to the local bus (local bus accesses are issued on the VMEbus).  All mappings are mapped one-to-one (a local bus access of 0xB0000000 is always converted to a VMEbus access of 0xB0000000 and vice versa).  The following two tables describe how these mappings are set.  Local to VMEbus Mappings:

VMEbus to Local Mappings:

Both the F-Page and the Short I/O map decoders are enabled.

The vmechip2 controls the local bus to VMEbus requester.  It is set so that VMEbus FAIR mode arbitration is used, the VMEbus is released when the transaction is completed, and the VMEbus request level has the value configured in the mvmecpu master.d file.  The bus grant timeout timer is enabled, VMEbus access timeout value is set to 32 milliseconds, the VMEbus global timeout value is set to 256 microseconds, and the local bus timeout value is set to 8 microseconds. 

The vmechip2 also controls various I/O related operations including DMA, a set of general purpose timers, and various local and VMEbus interrupts.  All DMA registers are set to zero.  Both timers’ registers on the vmechip2 are initialized to zero and timer 1 is set up as a free running clock.  The board control register is cleared, and the VMEbus control register word (0xFFF40048) has the MCLR bit (bit 11) set to 1 and all other bits reset to zero.  The RESET button, ABORT, ACFAIL, write posting, parity, and all VMEbus interrupt levels are enabled.  VMEbus interrupt request levels 1 through 7 are mapped to local interrupt request levels 1 through 7.  The VMEX and VMEY interrupt vectors (used for interrupts generated by the vmechip2 itself) are set based on the interrupt vector values in the VMEX and VMEY entries of the edt_data file. 

The pccchip2 controls all onboard peripherals.  The high order 4 bits of the interrupt vector used by each of the onboard devices is set based on the interrupt vector level specified for the PCC2 module in the edt_data file.  The two timers on the pcchip2 are initialized to an OFF state.  Timer 1 is used by the operating system as a time base and is reinitialized when the system clock is started.  General purpose I/O interrupts are disabled. 

Each memory mezzanine is controlled by an memc040.  Each of these has the bus clock register initialized based on the MPU speed and has parity detection and parity interrupts enabled. 

FILES

/dev/conctl
/dev/console
/dev/contty
/dev/contty??
/dev/dsk/m187_c0d?s?
/dev/e1x7_c0d0
/dev/generic/m187_c0d?
/dev/nvr∗
/dev/printer/lp187_c0d0
/dev/rdsk/m187_c0d?s?
/dev/rmt/m187_c0d?
/dev/xedt/lp1x7_c0
/dev/xedt/scsi1x7_c0

SEE ALSO

dcon(1M), mvmecpu(1M), scsi1x7(1M), console(7), cons1x7(7), e1x7(7), enet1x7(7), lp1x7(7), nvram(7), scsi1x7(7).