make Command make
Program building discipline
make [option ...] [argument ...] [target ...]
make helps you build programs that consist of more than one file
of source code.
Complex programs often consist of several object modules, each of
which is the product of compiling a source file. A source file
may refer to one or more include files, which can also be
changed. Some programs may be generated from specifications
given to program generators, such as yacc. Recompiling and
relinking complicated programs can be difficult and tedious.
make regenerates programs automatically. It follows a specifica-
tion of the structure of the program that you write into a file
called makefile. make also checks the date and time that
COHERENT has recorded for each source file and its corresponding
object module; to avoid unnecessary recompilation, make will
recompile a source file only if it has been altered since its ob-
ject module was last compiled.
***** The Makefile *****
A makefile consists of three types of instructions: macro
definitions, dependency definitions, and commands.
A macro definition simply defines a macro for use throughout the
makefile; for example, the macro definition
FILES=file1.o file2.o file3.o
Note the use of the equal sign `='.
A dependency definition names the object modules used to build
the target program, and source files used to build each object
module . It consists of the target name, or name of the program
to be created, followed by a colon `:' and the names of the ob-
ject modules that build it. For example, the statement
example: $(FILES)
uses the macro FILES to name the object modules used to build the
program example. Likewise, the dependency definition
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make Command make
file1.o: file1.c macros.h
defines the object module file1.o as consisting of the source
file file1.c and the header file macros.h.
Finally, a command line details an action that make must perform
to build the target program. Each command line must begin with a
space or tab character. For example, the command line
cc -o example $(FILES)
gives the cc command needed to build the program example. The cc
command lists the object modules to be used, not the source
files.
Note that if you prefix an action with a hyphen `-', make will
ignore errors in the action. If the action is prefixed by `@',
it tells make to be silent about the action -- that is, do not
echo the command to the standard output.
Finally, you can embed comments within a makefile. make recog-
nizes any line that begins with a pound sign `#' as being a
comment, and ignores it.
make searches for makefile first in directories named in the en-
vironmental variable PATH, and then in the current directory.
***** Dependencies *****
The makefile specifies which files depend upon other files, and
how to recreate the dependent files. For example, if the target
file test depends upon the object module test.o, the dependency
is as follows:
test: test.o
cc -o test test.o
make knows about common dependencies, e.g., that .o files depend
upon .c files with the same base name. The target .SUFFIXES con-
tains the suffixes that make recognizes.
make also has a set of rules to regenerate dependent files. For
example, for a source file with suffix .c and a dependent file
with the suffix .o, the target .c.o gives the regeneration rule:
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make Command make
.c.o:
cc -c $<
The -c option to the cc commands tells cc not to link or erase
the compiled object module. $< is a macro that make defines; it
stands for the name of the file that causes the current action.
The default suffixes and rules are kept in the files
/usr/lib/makemacros and /usr/lib/makeactions.
***** Macros *****
To simplify the writing of complex dependencies, make provides a
macro facility. To define a macro, write
NAME = string
string is terminated by the end-of-line character, so it can con-
tain blanks. To refer to the value of the macro, use a dollar
sign `$' followed by the macro name enclosed in parentheses:
$(NAME)
If the macro name is one character, parentheses are not neces-
sary. make uses macros in the definition of default rules:
.c.o:
$(CC) $(CFLAGS) -c $<
where the macros are defined as
CC=cc
CFLAGS=-V
The other built-in macros are:
$* Target name, minus suffix
$@ Full target name
$< List of referred files
$? Referred files newer than target
Each command line argument should be a macro definition of the
form
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make Command make
OBJECT=a.o b.o
Arguments that include spaces must be surrounded by quotation
marks, because blanks are significant to the shell sh.
Note that you can override any built-in macro by resetting its
value in the environment.
***** Options *****
The following lists the options that can be passed to make on its
command line.
-d (Debug) Give verbose printout of all decisions and informa-
tion going into decisions.
-f file
file contains the make specification. If this option does
not appear, make uses the file makefile, which is sought
first in the directories named in the PATH environmental
variable, and then in the current directory. If file is
`-', make uses the standard input; note, however, that the
standard input can be used only if it is piped.
-i Ignore all errors from commands, and continue processing.
Normally, make exits if a command returns an error.
-n Test only; suppresses actual execution of commands.
-p Print all macro definitions and target descriptions.
-q Return a zero exit status if the targets are up to date. Do
not execute any commands.
-r Do not use the built-in rules that describe dependencies.
-s Do not print command lines when executing them. Commands
preceded by `@' are not printed, except under the -n option.
-t (Touch option) Force the dates of targets to be the current
time, and bypass actual regeneration.
***** Files *****
makefile
Makefile -- List of dependencies and commands
/usr/lib/makeactions -- Default actions
/usr/lib/makemacros -- Default macros
***** See Also *****
as, cc, commands, ld, touch
The make Programming Discipline, tutorial
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make Command make
***** Diagnostics *****
make reports its exit status if it is interrupted or if an ex-
ecuted command returns error status. It replies ``Target name
not defined'' or ``Don't know how to make target name'' if it
cannot find appropriate rules.
***** Notes *****
The order of items in makemacros/.SUFFIXES is significant. The
consequent of a default rule (e.g., .o) must precede the an-
tecedent (e.g., .c) in the entry .SUFFIXES. Otherwise, make will
not work properly.
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