csync(2) DG/UX 5.4.2 csync(2)
NAME
csync - synchronize hardware caches for execute access
SYNOPSIS
#include <sys/types.h>
void csync (addr, len)
caddrt addr;
sizet len;
DESCRIPTION
The DG/UX system supports two methods for synchronizing hardware
cache and memory contents: issuing a trap to vector 502, defined by
the 88open Binary Compatibility Standard (BCS), revision 1.1A,
chapter 9; and csync(2), defined by the System V Release 4
Application Binary Interface (ABI): Motorola 88000 Processor
Supplement. If your program must be BCS-compliant, use the trap
method. Otherwise, use csync(2) as explained below.
The csync(2) call makes the designated memory region safe for
execution in all executable mappings of the region, and safe for
reading in all such mappings which have read and execute permission.
addr is the starting address of the memory region.
len is the length in bytes of the region.
If len is 0, all addresses are designated. If len is not 0, the
modulus sum of len and addr must exceed the value of addr. Otherwise,
the results are undefined.
On M88000 systems such as the AViiON, programs that modify and
execute memory need to invoke csync(2) just after the modification
and prior to the execution. Doing so notifies the system, and
synchronizes the contents of memory with that of the caches.
When several processes share a memory region, note:
⊕ Executable mappings of the shared region should include write
access, to insure that reading is always safe.
⊕ At least one of the processes must invoke csync(2), following
any modifications by the processes, and preceding execution by
any of them.
ACCESS CONTROL
None.
RETURN VALUE
None.
DIAGNOSTICS
None.
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csync(2) DG/UX 5.4.2 csync(2)
SEE ALSO
memctl(2), mmap(2), mprotect(2), stkexec(2), stkprotect(2).
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