NAME

cache − cache control and coherency

DESCRIPTION

Covers three topics related to the hardware caches on the systems:

1. System-wide control operations.  2. Per-process control operations. 3. Cache coherency. 4. Semaphores.

System-wide Cache Control Operations

On all systems, console processor commands (’y’ and ’td’) can be used to global disable the caches (instruction and data) or to disable architectural features of the caches (such as bursting or copyback accesses ).  A disabled cache or cache attribute cannot be re-enabled after the kernel has been booted. 

Per-process Cache Control

Series 4000 and 5000 systems support writethrough mode as well as copyback mode.  In copyback mode, a cpu write will usually only update the cache.  An immediate memory write is not performed.  At a later point, when the cache line is displaced or invalidated, the data will get written to memory.  The overall result is that the number of memory write operations is reduced.  This also decreases memory bus contention and memory latency. 

While copyback mode is optimal, it suffers from cache coherency problems on a Series 4000 resulting from DMA I/O transfers.  To overcome these problems, the kernel may need to perform expensive cache flush operations.  These operations could have a serious impact on interrupt and context switch latency.  The most severe problems occur when I/O is performed directly into a user copyback region (via direct or raw I/O).  For this reason, it is recommended that copyback mode not be used in such cases.  Note that these problems do not occur when using normal, buffered I/O. 

The Series 5000 caches are coherent with respect to I/O and therefore do not have to be flushed.  It is possible to use either copyback or writethrough regions. 

The text region of a process will ALWAYS use writethrough mode.  This cannot be altered.  The data and stack regions may use writethrough or copyback mode.  Users may specify the cache mode to use through use of the run(1) and rerun(1) commands (which call the memadvise(2) service).  A child process inherits the cache modes of its parent. 

By default, copyback mode will be used for the data and stack regions.  The system administrator can modify the default cache modes of all processes by altering the cache modes of the init(1M) process using rerun(1).  This is typically done as part of the /etc/rc script during system initialization. 

By default, shared memory regions will use writethrough mode, although an option to shmget(2) will allow the user to specify copyback mode.  On Series 4000 systems, copyback mode is not recommended for shared memory regions that are used for I/O purposes. 
Cache Coherency On some systems, I/O is not cache coherent.  As a result, dma from an I/O device to memory will result in stale data in the caches if any portion of the transfer buffer was cached.  One exception to this is local memory on Series 4000 systems.  This memory is kept cache coherent with I/O. 

On Series 5000 systems, a bus-watcher is used to keep the caches coherent with I/O devices. 

On all systems, a bus-watcher is used to keep the caches coherent in a multiprocessor environment.  Shared memory regions are cached, by default. There is an option when the shared memory region is created that specifies that it should not be cached.  Semaphores On Series 5000 systems, all semaphore operations must occur in cached memory.  The xmem instruction, which is used to construct test-and-set operations is not atomic except in cached memory.  See bsemget(2), Test_and_set(3c), spin_trylock(2), and server_block(2) for examples of routines which use this instruction.  The Series 4000 does not have this restriction. 

SEE ALSO

run(1), rerun(1) in the CX/UX User’s Reference Manual. 
memadvise(2) in the CX/UX Programmer’s Reference Manual. 

CX/UX Administrator’s Reference